Integrated circuits (ICs) are generally fabricated in an array on or in a semiconductor substrate. For example, FIG. 1 is a perspective view of a typical semiconductor wafer 100 having a plurality of ICs 110 formed thereon. The ICs 110 are separated by dicing lines or streets 112 that form a lattice pattern on a top surface of the semiconductor wafer 100.
The ICs 110 are singulated by mounting the back side of the semiconductor wafer 100 on a tape frame (not shown) and cutting along the streets 112 formed on the top surface of the semiconductor wafer 100. Cutting is generally carried out by a cutting machine called a dicer that includes a chuck table for holding the semiconductor wafer 100 and a mechanical saw or laser for cutting the semiconductor wafer 100. Mechanical saws generally include a rotary spindle and a cutting blade mounted on the spindle. The cutting blade may include, for example, a disk-like base and an annular cutting edge fitted to the outer peripheral portion of the side surface of the base. The cutting edge generally includes diamond abrasive grains.
The streets 112 are generally visible from the top side of the semiconductor wafer 100. Thus, from the top side of the semiconductor wafer 100, the mechanical saw or laser may be guided along the streets 112 to cut the semiconductor wafer 100 into individual ICs. The tape frame, also referred to as dicing tape, holds the ICs 110 in place during and after the dicing process. However, the top surface of the ICs 110 are left unprotected during the dicing process and may be damaged by the mechanical saw or laser. For example, metals, low-k dielectrics, or other materials formed in the streets 112 on the top surface of the semiconductor wafer 100 can damage the ICs 110 and/or the mechanical saw.
FIG. 2 is an enlarged top view of the semiconductor wafer 100 shown in FIG. 1 illustrating metal features 210, 212 formed in the streets 112 on the top surface of the wafer. The metal features 210, 212 may include, for example, coupons or test circuits used during the manufacturing process and sacrificed when the semiconductor wafer 100 is diced. A test circuit may include, for example, a metal pattern called a test element group (Teg) applied over the semiconductor substrate 100. The metal features 210, 212 tend to clog or otherwise damage diamond impregnated saws typically used in the dicing process. Mechanical sawing produces burrs because a Teg, for example, is generally made of a soft metal such as copper or the like. In addition, as thinner wafers are produced, mechanical saws cause more edge chipping. Thus, yield (e.g., the number of functioning ICs produced from the wafer) decreases.
Laser dicing can also damage the ICs 110 and reduce yield. Instead of using a traditional saw blade, a laser beam is focused onto the top surface of the semiconductor wafer 100 to thereby “cut” the semiconductor wafer 100 into the individual ICs 110. The process of laser dicing generates excessive heat and debris. The heat can cause heat affected zones and recast oxide layers. Cracks may form in the heat affected zones and reduce the die break strength. Further, the debris produced by lasers is molten in one state and can be very difficult to remove. Sacrificial coatings can be used to protect the top surface of the ICs 110 from debris during laser dicing. The sacrificial coating must then be removed after the dicing process. Another process uses a water jet in conjunction with the laser. The water jet washes the debris away during the dicing process. However, sacrificial coatings and water jet or other cleaning processes add time and expense to the overall dicing process.
Therefore, a method of dicing finished semiconductor wafers that increases throughput and yield is desirable.